1. Field of the Invention
The present invention relates to a precharged-type logic circuit, and particularly to a precharged-type logic circuit which can be operated at a high speed.
2. Description of the Prior Art
FIG. 1 is a compositional diagram of a synchronous type PLA1000 in order to show an example of a conventional precharged-type logic circuit. In the same drawing, reference characters .phi. 1 and .phi. 2 show clocks to be respectively given to an AND plane as the AND array and an OR plane as the OR array, and reference numeral 1010 designates an input line for inputting a logic level, and 1011 and 1012 show a product term line and an output line, respectively, further V.sub.DD designates a power source.
The AND array is composed of the plurality of input lines 1010, NMOS transistors N1 and the product term lines 1011. While, the OR array comprises the output lines 1012, NMOS transistors N.sub.2 and the product term lines 1011.
FIG. 2 shows an operational timing chart of the PLA1000 having the above-mentioned composition. In the same drawing, the precharge operation of the product term lines 1011 is started at the rising time of the clock .phi. 1 rises. After a time interval tp has passed (in which the electric potential of all the product term lines has reached a predetermined L (Low) level) from the time of the falling edge of the clock .phi. 1, a read operation of the output lines 1012 is started at the falling edge of the clock .phi. 2. Accordingly, when the time difference between the times of the falling edges of the clocks .phi. 1 and .phi. 2 is expressed by .DELTA. t, .DELTA. t and tp is set in the relation represented by .DELTA. t&lt;tp.
By the way, in order to improve the operation speed of the PLA1000, it is necessary to set the clock frequency of the clocks .phi. 1 and .phi. 2 high. However, when the frequency becomes high, operational errors are related likely to be caused in detection or determination of the time difference between the clocks .phi. 1 and .phi. 2. Therefore, in this case, high accuracy control of the time difference .DELTA. t of the clocks .phi. 1, .phi. 2 should be required. As the result, the composition of a clock control circuit for realizing such high-accuracy time difference control must be extremely complicated.
On the other hand, since tp is the time delay caused in the PLA1000, it is very difficult to precisely control tp as well as .DELTA. t. Therefore .DELTA. t must be set a little wider than a required value advance. Accordingly, the start time of read of the output lines 1012 is also delayed so much, so that the operation efficiency of the PLA1000 is degraded.
Moreover, such difficulty in precisely controlling .DELTA. t and tp is likely to cause timing errors in setting periods for precharge of the product term lines and the output lines, so that it is very difficult to control the timings of precharge and read operation under high-speed operational conditions.
As described above, in the PLA as the conventional precharged-type logic circuit, all of the operations are executed by control based on the rising edge and falling edge of the control clock. Accordingly, it is difficult to perform it at high speed, so that the operational efficiency of the logic circuit becomes low. In addition, the clock circuit for generating the two kinds of control clocks given the PLA is complicated.